Concurrent error correction in systolic architectures
Romain Cosentino · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1988
It is shown how two features of systolic arrays in which the cells retain partial results rather than pass them on can be used to facilitate testing and fault localization with no modification of the systolic design; the monitoring is performed either by software in the host processor or by hardware following the system output. One feature is the ability to enter identical sequences of inputs into two adjacent processor elements; the other is the resemblance of the data flow to that of a scan design. In particular, a one-dimensional systolic architecture of interest is described and applied to a finite-impulse response filter. Both the error detection and correction coverages are considered in detail for the FIR filter. The concurrent error-correction technique is applicable only to operational reliability, but the concurrent error-detection technique is equally applicable to manufacturing tests, incoming tests, and periodic maintenance tests. A hardware implementation of the error-detection-and-correction technique is presented. The architecture is extended to a two-dimensional processor.>