Compilation for FPGA-based reconfigurable hardware
João M. P. Cardoso, Horácio C. Neto · IEEE Design & Test of Computers · 2003
This paper provides techniques for compiling software programs into reconfigurable hardware which offer faster and more efficient performance than the complex resource-sharing approaches typical of high-level synthesis systems. The Java-based compiler presented in this paper uses intermediate graph representations to embody parallelism at various levels.