An integrated building block for fast digital filtering
V. Rebmann, Jörg Heinrich, Ernst Lüder · 2003
A 2.4- mu m CMOS chip is presented for realizing a programmable building block for second-order recursive digital filters. All the fabrication steps lend themselves to high-volume production. Using a fast algorithm, a highly parallel computing scheme, and new algorithmic circuits, the chip allows for a maximum clock frequency of 18 MHz, thus being able to compute every second-order filter function in 56 ns with internal 16-bit fixed-point precision. By cascading several chips, filters of higher degree can be obtained without loss of speed.>