Scheduling in input-queued cell-based packet switches
Marco Ajmone Marsan, Andrea G. Bianco, Paolo Giaccone, Emilio Leonardi, F. Neri · 2003
Input queuing switch architectures must be controlled by a scheduling algorithm, which solves contentions in the transfer of data units from inputs to outputs. Several scheduling algorithms were proposed in the literature for switches operating on fixed-size data units. We consider the case of packet switches, i.e., devices operating on variable-size data units at their interfaces, but internally operating on fixed-size data units, and we propose novel extensions of known scheduling algorithms. We show that, in the case of packet switches, input queuing architectures can provide advantages over output queuing architectures.