A bit-serial cell for reconfigurable DSP hardware
Mitchell J. Myjak, Jose G. Delgado-Frias · 2005
This paper introduces a novel bit-serial cell for reconfigurable hardware used to perform digital signal processing. The cell contains an array of 4-bit lookup tables, or "elements" that can operate in two modes. In memory mode, the elements behave as a random-access memory. In mathematics mode, the elements perform operations such as multiply-accumulate, addition, and shifting in bit-serial fashion. To calculate m-bit functions, the cell requires (m+ 1) elements and (2m + 1) clock cycles. Layout simulations in 180-nm CMOS demonstrate that the serial clock frequency approaches 2 GHz. Compared to a parallel implementation with the same functionality, the cell has lower throughput but substantially smaller area.