A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS
Mark A Anders, Himanshu Kaul, Martin Hansson, Ram Kumar Krishnamurthy, Shekhar Y. Borkar · 2008
An on-die multi-core circuit-switched network for tera-scale computing, achieving 2.9 Tb/s throughput for random data transmissions on a 64 core 2D mesh and consuming 8 W in 45 nm CMOS at 1.0V, 50degC is described. Use of pipelined circuit-switched transmission, coupled with circuit path queue circuits and packet-switched request circuits enable power consumption of 125 mW/router and efficiency of 363 Gb/s/W, with scalable traffic-dependent throughput up to 6.2 Tb/s.