Test generation for VLSI chips with embedded memories
E. Kofi Vida-Torku, J.A. Monzel, T. L. Bossis, Charles E. Radke, D.M. Wu · IBM Journal of Research and Development · 1990
An effective approach for generating patterns for testing memories embedded in logic is presented. Through circuit testability analysis, which is a study of the effect of process defects on memory circuits, unique algorithms can be derived for testing the memory. Circuit and logic designs for test features that are required to make the pattern generation process optimal are discussed. An analytical method is described which assesses the performance characteristics of the memory after functional test.