A parallel pipelined DSP processor core
Valentine C. Aikens, Jose G. Delgado-Frias, G.G. Pechanek, Simon Vassiliadis · 2002
In this paper a novel high performance processor is presented along with its applicability to digital signal processing. The generic sum of product processor organization contains three major sections: parallel, reduction, and multifunction generator. Each of these sections works in a pipelined fashion providing extremely high performance. We have studied a number of digital signal processing algorithms and mapped them onto the proposed processor. We report the mapping of three of the most widely used algorithms: convolution, discrete Fourier transform, and discrete cosine transform. In order to evaluate the potential impact of the processor, we have included a performance comparison with other digital signal processing machines. The proposed processor performs extremely well using a small amount of hardware.