Fault diagnosis for static CMOS circuits
Wen Xiaoqing, Hideo Tamamoto, Kewal K. Saluja, K. Kinoshita · 2002
This paper presents a new methodology for transistor leakage fault diagnosis using both I/sub DDQ/ and logic information. A method for handling intermediate faulty voltages in fault simulation is proposed. A scheme for generating diagnostic test vectors based on logic information in the presence of intermediate faulty voltages is also proposed. An example is used to demonstrate the new diagnosis methodology.