A 200-MHz 64-b dual-issue CMOS microprocessor
D.W. Dobberpuhl, Richard T. Witek, R. Allmon, Robert Anglin, David Bertucci, Sharon M. Britton, L. Chao, R. Conrad, D.E. Dever, B. Gieseke, Soha Hassoun, G.W. Hoeppner, Kathryn Kuchler, Maureen Ladd, Burton M. Leary, Liam Madden, E. J. McLellan, Derrick Meyer, J. Montanaro, Donald A. Priore · IEEE Journal of Solid-State Circuits · 1992
A 400-MIPS/200-MFLOPS (peak) custom 64-b VLSI CPU is described. The chip is fabricated in a 0.75- mu m CMOS technology utilizing three levels of metalization and optimized for 3.3-V operation. The die size is 16.8 mm*13.9 mm and contains 1.68 M transistors. The chip includes separate 8-kbyte instruction and data caches and a fully pipelined floating-point unit (FPU) that can handle both IEEE and VAX standard floating-point data types. It is designed to execute two instructions per cycle among scoreboarded integer, floating-point, address, and branch execution units. Power dissipation is 30 W at 200-MHz operation.>