Clock-tree routing with single buffer-block allocation strategy
Chuen-Yau Chen, Pei-Chia Yang · 2005
In this paper, we propose a method combining the concepts of buffer-insertion with global-routing to build a zero-skew clock tree with less latency. First, we allocate a single buffer-block for buffer insertion in the chip. Perform global routing by treating the single buffer-block as the same as the other building blocks. Estimate the wire loads and determine the number and size of the buffer to be inserted in each path. This approach can achieve a zero-skew clock tree with a lower routing complexity. The simulation results have verified the feasibility.