An instruction timing model of CPU performance
Bernard L. Peuto, Leonard J. Shustek · 1998
A model of high-performance ccmputers is derived from instruction timing formulas, with Empensation for pipeline and cache memory effects.The model is used to predict the performance of the IEh 37C/168 and the AmdaN 470 V/6 on specific programs,,and the results are verified by cunpacison with actual performance.Data collected about program behavior is combined with the performance analysis to highlight some of the problems with high-performance implementations of such architectures.