A VLSI design of a high-speed Reed-Solomon decoder
Hanho Lee · 2002
Reed-Solomon (RS) codes have been widely used in a variety of communication systems to protect digital data against errors occurred in the transmission process. This paper presents a VLSI implementation of a high-speed 8-error correcting, RS(255,239) decoder architecture using a modified Euclidean algorithm for communication systems. The RS decoder has been designed and implemented with a 0.16-/spl mu/m CMOS standard cell technology with a supply voltage of 1.5 V. The results show that the proposed RS decoder operates at a clock frequency of 670 MHz and has a data processing rate of 5.36 Gbit/s.