An efficient model for DSP code generation: performance, code size, estimated energy
Catherine H. Gebotys · 1997
This paper presents a model for simultaneous instruction selection, compaction, and register allocation. An arc mapping model along with logical propositions is used to create an optimization model. Code is generated in fast cpu times and is optimized for minimum code size, max-imum performance or estimated energy dissipation. Code generated for realistic DSP applications provide perfor-mance and code size improvements from 1.09 up to 2.18 times for the TMS320C2x processor compared to previous research and a commercial compiler. In all examples up to 106 instructions are generated in under one cpu minute. This research is important for industry since DSP code can be efficiently generated with constraints on code size, per-formance, energy dissipation.