A token scan architecture for low power testing
Tsung‐Chu Huang, Kuen-Jong Lee · 2002
Presents a novel scan architecture for low-power testing, which employs the techniques of multiphase clocking, token ring, and clock-gating. When the multiphase clocking technique is directly employed to a scan chain, inter-phase skews and large routing area will be the problems. We develop a token scan cell design to address these problems. To reduce the power dissipation due to the clock and scan-in data trees, we propose a novel clock-gating technique that takes advantage of the regularity and periodicity of the token scan chain. Combining the three techniques, the token scan architecture can efficiently reduce the data transitions in the scan circuits as well as the switching activity in both the clock and the scan-in data trees. From experiments, more than 95% of power reduction can be achieved for most circuits with long scan chains.