Mining AC delay measurements for understanding speed-limiting paths
Janine Chen, Brendon Bolin, Li-C. Wang, Jing Zeng, Dragoljub Gagi Drmanac, Michael Mateja · 2010
Speed-limiting paths are critical paths that limit the performance of one or more silicon chips. This paper present a data mining methodology for analyzing speed-limiting paths extracted from AC delay test measurements. Based on data collected on 15 packaged silicon units of a four-core microprocessor design, we show that the proposed methodology can efficiently discovered actionable, design-related knowledge that would be difficult to find otherwise.