The art of numbers
C. Edwards · Electronic Systems and Software · 2007
Programmable logic and high-resolution maths do not mix that well. Field programmable gate arrays (FPGAs) did not start out as high-speed maths engines. Initially, they were very slow at multiplies because the only efficient architecture they could use was the bit-serial multiplier. Although efficient on a conventional FPGA, the bit-serial multiplier is very, very slow. As FPGAs grew, they added hardwired multipliers that could be combined to build much faster maths engines. However, there are still restrictions on how much you can squeeze into an FPGA cost-effectively. This paper discuss ways to squeeze more efficiency out of the devices.