A scalable architecture for discrete wavelet transform
Sibtain Syed, Magdy Bayoumi · 2002
We present the design and prototyping of an efficient systolic architecture which performs both forward and inverse discrete wavelet transform. The proposed architecture consists of a linear array of processing elements, each of which has an adder and a multiplier and fixed number of I/O channels. The wavelet transform is computed by convolution and by mapping the computation on to a linear array of systolic processing elements. The design of the architecture has been shown to be simple, scalable and has the advantage of low I/O bandwidth. The number of processing elements is independent of the size of the input. The architecture has been prototyped using 2/spl mu/m p-well CMOS technology and has been developed in the CADENCE Edge Design Framework environment.