Hardware architecture for accelerating communication on Maestro3 cluster network
Hiroki Inoue, Koichi Wada, Hajime Kuribayashi, Koji Yasuda, Masaaki Ono · 2009
This paper presents architecture for accelerating message switch and synchronization performed in a message passing library developed on Maestro3 cluster network. Maestro3 is a high-performance cluster network that has the optimized data link layer and the capability of dynamic offload. We propose the dedicated hardware for further improvement of communication performance. In this paper, detailed analysis of overheads in message switch and in synchronization is described. Architecture and implementation of the proposed hardware are presented in detail. Evaluation has been performed by comparing performance of software approach and the proposed hardware approach. The results of evaluation showed that the latency of message switch and synchronization have been reduced by the proposed hardware to 8% and 22%, respectively.