Multi-Bank Register File for Increased Performance of Highly-Parallel Processors
Koh Johguchi, Ken-ichi Aoyama, Tetsuya Sueyoshi, Hans Jürgen Mattausch, Tetsushi Koide, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa · Proceedings of ESSCIRC · 2006
A multi-bank register file architecture for increasing the register-access clock frequency by up to 95 % and an access arbitration method for avoiding degradation of the cycle number based processor performance are reported. A 4-bank test design in 200 nm gate-length CMOS with 12 ports and 128 registers has 0.39 mm2area and operates at up to 417 MHz