MPEG-4 video codec IP design with a configurable embedded processor
Jin‐Gyeong Kim, C.‐C. Jay Kuo · 2003
Design of the MPEG-4 video codec IP (intellectual property) module with a configurable embedded processor architecture for the system-on-chip (SoC) application is presented in this research. First, we perform platform independent software optimization, in which the algorithmic optimization is conducted to improve the software performance for a general-purpose processor (GPP). Then, we obtain further performance improvement with the instruction-level hardware optimization, which is tailored to a configurable embedded processor architecture. The software optimization can be used in any application while the optimized instructions for video processing can be used in other video compression standards such as MPEG-1/2 and H.26L. With the two-step optimization approach, a significant performance improvement is achieved with high flexibility. In our experiment, the speed of the MPEG-4 simple profile level 1 (SP/L1) encoder is improved by 71 times. The developed IP enables the SoC design for multimedia applications within a short development period.