The design and testing of an analogue neuron
W.A.J. Waller, D.L. Bisset, P. M. Daniell · 1991
Describes a neural architecture which requires a low number of I/O connections and can be used directly with scanned data sources. The circuits used and the testing of the device are also described. The Frame Based Architecture is a cascadable neural network implementation architecture. It is capable of computing fully connected networks in real time with frame based data sources and externally stored weights. This is achieved without speed or device interconnect penalties. The device is a full-custom chip which has been fabricated using a standard CMOS process. It demonstrates satisfactory operation of weight multiplexing and of the double buffered shift register output. Work is now progressing towards a multi-chip demonstrator and the replacement of the pulse based multiplier by a four quadrant analogue design. >