Seamless - a latency-tolerant RISC-based multiprocessor architecture (abstract)
Samuel A. Fineberg, Thomas L. Casavant, Brent H. Pease · 1992
The Seamless parallel system being developed at the University of Iowa ECE Department provides a method for providing latency tolerance in physically-distributed memory systems utilizing “off-the-shelf” RISC CPU's without incurring the overhead of multithreading. Seamless encompasses an evolutionary new programming model emphasizing data locality that views communication as data movement rather than message passing I/O. A hardware Locality Manager is added to each processing element to perform this data movement concurrently with computation.