Resource and delay efficient matrix multiplication using newer FPGA devices
Scott J. Campbell, Sunil P. Khatri · 2006
Matrix multiplication is a fundamental building block for many applications including image processing, coding, and digital signal processing. This paper presents a delay and resource efficient methodology for implementing integer and floating point matrix multiplication using FPGAs. We present a scalable architecture that provides a significant reduction in total computation time and resource utilization over previous solutions. The improvements of our method are attributed to a new method to compute partial products in parallel, utilizing the new features of modern FPGAs. The implementation of our algorithm for various matrix dimensions using Xilinx FPGAs is also described. When compared with the best reported previous method, our approach achieves an improvement in the parallelization of 60% for 64-bit floating point computations.