Fault models and tests for a 2-bit-per-cell MLDRAM
M. Redeker, B.F. Cockburn, Duncan G. Elliott · IEEE Design & Test of Computers · 1999
Multilevel DRAM technology may become a cost effective way to increase semiconductor memory storage density. The authors develop an MLDRAM fault model using both manual analysis and analog simulation. They also propose several alternative testing strategies and possible design-for-testability enhancements.