Estimating Area Efficiency of Antifuse based Channeled FPGA Architectures
Mahesh M. Mehendale · 2005
The paper presents a scheme for estimating area efficiency of antifuse based channelled FPGA architectures. It enables evaluating logic module alternatives differing in granularity and functionality, so as to develop an architecture thatis optimum in terms ofarea. The area efficiencygives the estimate of silicon area required by an FPGA architecture to realize designs of the specified gate capaciiy, The two major components of the area are the logic module array and the routing resources. The paper describes techniques for estimating both these components and presents results for five logic module architectures. The results are analyzed to show the effect of logic module granularity and combinational - sequential logic mix of the designs, on the area efficiency.