A new BIST scheme for CMOS PLAs
V. Chandramouli, R.K. Gulati, Ramaswami Dandapani · 2002
A novel BIST (built-in self-test) design that detects stuck-at, stuck-on, stuck-open, and bridging faults in CMOS PLAs (programmable logic arrays) is presented. I/sub DDQ/ testing is used for detecting bridging faults. The overhead is comparable to that of existing BIST schemes. The testing can be performed at normal system speed. A PLA-size-independent BIST controller was implemented and tested on a number of industrial PLAs.