Predicting pipelining and caching behaviour of hard real-time programs
Friedhelm Stappert · 2002
A new system for the instruction level timing analysis of hard real time programs is presented. The analysis exploits the very simple structure of these programs, resulting in a considerable processing time improvement compared to general case analysis techniques. The new analysis system covers all speed up mechanisms used for modern superscalar processors at once: pipelining, data caching and instruction caching. The analysis can handle a unified cache as well as separate caches for data and instructions.