Efficient encoding of instructions of ARM Cortex M0+ processor
Gennaro De, Paulius Stankaitis · School of Computing Science Technical Report Series · 2015
As the complexity of digital hardware grows steadily, so does the demand of high level modelling systems to abstract the low level implementation of synchronous and asynchronous digital circuits. Conditional partial order graphs representation provides a compact and solid approach to represent event-based systems, and together with Workcraft design tool, they represent an extremely efficient development environment to create any system. So far, the synthesis phase of the controller for managing the whole datapath structure lacked an efficient encoding association mechanism, as well as a friendly and customisable user interface to encode the Partial order graphs. The following paper aims at bridging this gap, providing a graphical user interface integrated in Workcraft, new algorithms for the generation of encodings for the Partial orders composing the system and the possibility to customise the final op-codes, if needed. All these features have been tested on the Instruction Set Architecture ARMv6-M, integrated into the ARM Cortex M0+ microprocessor showing quite a big improvement in terms of area of the final controller with respect to previous approaches.