High speed IDDQ test and its testability for process variation
Masaki Hashizume, Hiroyuki Yotsuyanagi, Masakazu Ichimiya, T. Tamesada, M. Takeda · 2002
A new high speed IDDQ test method is proposed. It is based on charge current for load capacitances of gates whose output logic values are changed from L to H by test input vector application. In this paper, the testability of the test method is examined for some process variations generated in CMOS IC production.