Programmable traffic generator with configurable stochastic distributions
A. Abdo, Trevor J. Hall · 2006
Our aim in this paper is to present a field programmable gate array-based traffic generator using a dedicated microprocessor within a configurable device (Stratixcopy from Altera). The traffic consists of fixed-size packets at a bit rate of 50 Mbps and three different patterns of network traffic in order to emulate the non-stationarity and bursty nature of real network traffic. The design makes use of the features offered by the Nios board, Stratix Edition, chosen as development platform, and the advantages of system on a programmable chip (SOPC) builder provided by Altera. The applications of this module are numerous, especially in the performance testing of the new generation of high-speed network switching module (e.g. layer 2 switches)