Rank-order filtering algorithms: A comparison of VLSI implementations
Jan Narkiewicz, Wayne P. Burleson · 1993 IEEE International Symposium on Circuits and Systems · 2002
A new method is used for evaluating the VLSI area/time tradeoffs of rank-order circuits. Rather than relying on asymptotic analysis, a variety of both full and approximate algorithms are actually implemented and compared. Oct, a high level synthesis tool, is used in order to provide a level playing field on which to evaluate each approach. In addition to various data widths and number of elements ranked, designs are parameterized based on the format in which data is input and output. This three-dimensional problem space is combined with an extensive design space from the literature, and provides new insights into the realistic costs associated with rank-order filtering.>