Predicting system-level area and delay for pipelined and nonpipelined designs
Rajiv Ratan Jain, Alice C. Parker, N. Park · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1992
The ability to predict area-delay characteristics of designs without actually implementing them is important in producing quality designs in a reasonable time. A mathematical model for predicting the area-delay tradeoff curve for pipelined and nonpipelined data paths, given a data flow graph and a choice of module styles, is proposed. The model has been validated against designs generated by pipelined and nonpipelined data-path synthesis programs.>