A bit-serial systolic algorithm and VLSI implementation for RSA
C.N. Zhang, Yin Xu, Cheng-Yen Wu · 2002
A new algorithm using delayed save adder representation and overflow determination technique for modular multiplication is presented. This algorithm can be implemented by a bit-serial systolic array for modular multiplications. A two level bit-serial systolic array for RSA is also designed and implemented. Our simulation and experimental chip design show that the proposed algorithm and its bit-serial implementation is suitable for VLSI, and a single RSA chip can be built to achieve much higher throughput.