A digital filter code generator with automatic scaling of internal variables
João Francisco Martins · 1993 IEEE International Symposium on Circuits and Systems · 2002
A digital filter code generator for fixed point digital signal processors is described. The approach used is directed towards the optimization of the filter graph, including automatic scaling of internal variables and redundant node elimination, and has been followed on a computer program called SFGC (Signal Flow Graph Compiler). Several analyses, such as frequency response, sensitivity analysis, noise analysis, time response simulation with integer and floating point arithmetic, can be performed by this program. The techniques used to implement the program are described.>