A Repartitioning and HW/SW Partitioning Algorithm to the Automatic Design Space Exploration in the Co-Synthesis of Embedded Systems
Francisco Assis Moreira do Nascimento, Wolfgang Rosenstiel · Symposium on Integrated Circuits and Systems Design · 2001
Abstract: We present a co-synthesis algorithm that combines repartitioning and HW /SW partitioning of the processes in a system specification to provide an efficient design space exploration stractegy. The algorithm is defined on a Partial Order based Model (POM), which is an alternative to model concurrency at a high level of abstraction and has a concise symbolic representation, mainly for systems with high degree of parallelism, as well as allows the use of efficient reachability analysis techniques based on partial order reductions. Our repartitioning algorithm generates a partitioning tree, where the possible partitions of the processes in a specification are represented in a systematic way, according to the communication among them. The HW /SW partitioning algorithm is applied on these possible partitionings and will select the one that minimizes the communication cost between the partitions. In this paper, we will just present the repartitioning: HW /SW partitioning and performance/cost estimates algorithms and how they are used in our design space exploration stractegy. The reported experimental results show the efficiency: when compared with related works: and practicability of our co-synthesis algorithms.