Testing the hold time fault for large industrial design
Kun-Han Hans Tsai, Janusz Rajski · 2008
A new fault model and ATPG algorithm are proposed to target the hold time fault, which is guided by the timing information (e.g. from SDFfile) to detect the fault through the shortest path to maximize the probability of detecting the hold time fault due to small delay defects or process variations. The fault population is linear to the number of the state elements in the design and the fault list is automatically derived by the algorithm, which makes the solution robust and practical on large design over 10M gates.