Design of a one-transistor-cell multiple-valued CAM
Takahiro Hanyu, Naoki Kanagawa, Michitaka Kameyama · IEEE Journal of Solid-State Circuits · 1996
A new high-density multiple-valued content-addressable memory (CAM) is proposed to perform highly parallel search operations in a limited chip area. The number of cells in the CAM is reduced by the use of multiple-valued data representation. Moreover, multiple-valued stored data correspond to the threshold voltage of a floating-gate MOS transistor, so that the cell circuit can be designed using only a single transistor. As a result, the cell area of the proposed four-valued CAM is reduced to 14% of that of a conventional dynamic binary CAM, and its performance is about 5.4-times higher than that of the corresponding binary one under a 0.8-/spl mu/m standard EEPROM technology.