A 50 MIPS multiprocessor chip for image processing
Tony Denayer, Etienne Vanzieleghem, P. Jespers · 2003
A 50-MIPS (million-instruction-per-second) 90000-transistor CMOS multiprocessor chip is described. It has been designed as a building block for orthogonal transforms of TV images in a bandwidth-reduction system. 64 processing elements (serial parallel multipliers) are assembled in a systolic-like architecture. Because of its modularity, the chip can be used for matrix products of arbitrary size.>