A Multi-level Reconfigurable Architecture for a Wireless Sensor Node Coprocessing Unit
François Philipp, Manfred Glesner · 2011
An architecture for a dynamically reconfigurable co processing unit for a wireless sensor node is presented in this paper. The hardware accelerator is tailored for the processing of sensor data streams that cannot be efficiently handled by low-power micro controllers. High energy-efficiency is obtained by using reconfigurable computing mechanisms. The details of the architecture including multiple, specialized, reconfigurable processing stages are introduced. For a fast and efficient dynamic reconfiguration, the size of the reconfiguration data is minimized by using multiple reconfiguration levels. Reconfigurable function units are reused for the implementation of different algorithms sharing arithmetical properties. Thus, only a few resources are required for reconfiguration, limiting the power consumption of the node while its computation performance is increased with application-specific accelerators. An application example illustrates the utilization of the processing unit for the acquisition of accelerometer data.