A virtual zero-time, monolithic systolic sorting array
M.N. Ericson, C.L. Britton, D.W. Bouldin · 2002
A virtual zero-time VLSI sorting chip is described. The chip SORTPIPE II has a systolic array architecture and implements the sinking sort algorithm. The basic functional module of the systolic array is detailed, and development techniques employed as well as functional simulation and results are presented.>