A wafer scale programmable systolic data processor
David L. Landis, John Yoder, Dustin Whittaker, T. Dobbins · 2002
The authors describe the programmable systolic data processor (PSDP). The PSDP will enhance US Department of Defense (DoD) mission capabilities by extending signal and data processing speed/performance while reducing system size, weight, and power consumption. The characteristics of this architecture which make it opportune for building as a wafer-scale system include broad homogeneity, ease of redundancy, and limited physical interconnect bandwidth of wafer-scale integration (WSI) using a robust programmable systolic array processing architecture. Thus, it will provide unique onboard processing capabilities for DoD missions.>