PAR-BS based predictive row close memory scheduler for DRAM
Kautilya Aswal · CSUN ScholarWorks (California State University, Northridge) · 2013
In a Chip Multiprocessor System (CMP) DRAM system is the one, which is shared by the multiple cores of the system.Each core has several threads running on them.Request from a thread, cannot only delay request from other threads but can also destroy the request from other threads as well.The primary reasons can be- Bank Conflicts Bus Conflicts Row Buffer Conflicts As the gap between memory and processor performance continues to widen, it becomes imperative that new techniques, which improve memory performance, be proposed.This research describes the functioning of our high-performance Memory scheduler.The scheduler implements a parallelism aware batch-scheduling algorithm (PAR-BS).This research takes ideas from existing scheduling heuristics and combines them with