Towards a faster simulation of SystemC designs
Ahmad Rizky Nusantara Habibi, Haja Moinudeen, Amer Samarah, Sofiène Tahar · 2006
Accelerating simulation is one of the main reasons beyond the introduction of system level modeling. Here SystemC is one of the main players proven to speed-up simulation in comparison to classical HDL languages. However, the kernel architecture of the SystemC simulator treats the design as a black box. For instance, all active processes are executed without checking if they are relevant to the test plan. We illustrate the performance of our approach on a set of models built on top of the master/slave library part of the SystemC release and for two levels of abstraction: untimed functional (UTF) and bus-cycle-accurate (BCA)