Variance reduction using wafer patterns in I/sub ddQ/ data
W.R. Daasch, James McNames, Dan Bockelman, K. Cota · 2002
The subject of this paper is I/sub ddQ/ testing for deep sub-micron CMOS technologies. The key concept introduced is the need to reduce the variance of good and faulty I/sub ddQ/ distributions. Other I/sub ddQ/ based techniques are reviewed within the context of variance reduction. Using the SEMATECH data and production data, variance reduction techniques are demonstrated. The main contribution of the paper is the systematic use of the die location and patterns in the I/sub ddQ/ data to reduce variance. Variance reduction is completed before any I/sub ddQ/ threshold limits are set.