Performance driven BIST technique for random logic
Charles A. Njinda, Neeraj Kaul · 2002
Performance degradation due to insertion of BIST logic into high-speed designs has been analyzed. A framework to introduce BIST into random logic circuits, without causing timing violations has been proposed. Various heuristics for selecting flip-flops for BIST have been developed and studied in detail. Experimental results indicate an improvement in performance while optimizing fault coverage and area overhead.