3-D stacked NAND flash memory having lateral bit-line layers and vertical gate
Ju-Wan Lee, Min-Kyu Jeong, Byung‐Gook Park, Hyungcheol Shin, Jong‐Ho Lee · 2012
In this paper, we have studied a new 3-D stacked NAND flash memory structure and explained the fabrication sequence and key features of fabricated devices. Reasonable operation of the devices was shown in terms of ΔVth, retention and cycling characteristics. Moreover, the device characteristics were quite improved by removing the etch damage on the side surface (channel) of poly-Si BL layers when CDE process was adopted after etching the BL stack.