A Scheme For Synthesizing Testable Vlsi Designs With Minimum Area Overhead
B. Mitra, P.P. Chaudhuri · 2005
In contrast to conventional design and test approaches where testability is considered after the design phase, the scheme presented here selects efficient test configurations in the ear& stages of design synthesis. The integrated appmach presented here aims at arriving at a synthesized design with minimum area overhead. THE SCHE ME Theschemetakesaslnput, adataflow graph (DFG) (derived from a VHDL description) that serves as the input to the datapath synthesis system. Given a DFG, we have used a stochastic evolution [l J based optimization scheme for simultaneous scheduling, allocation and binding of the datapath architecture. The first step in this procedure is the creationof a resource-control step matrix from the DFG. A Finite State Machine (FSM) description for controlling this datapath is next generated from the original VHDL description and the datapath architecture being evaluated. In view ofthe high computational complexity associatedwith synthesizingthe FSM at every iteration, we have developed a scheme to estimate the complexity of the control logic directly [2] from the FSM spedfications. The stochastic evolutionscheme incorporates test synthesis procedures in every iteration of the optimization step to ensure that a datapath architecture is finally selected which is not only testable, but forwhich the total area (includingthe test area overhead) is minimum. Since most test synthesis systems described in the past are extremely computation intensive, applying these in the optimization loop of stochastic evolution has been found to be very ineffident. Instead, we have developed several efficient heuristics for test synthesis that configures the candidatedatapatharchaecturesfortest. The test area overhead associated with every such candidate architecture is determined by adding the