An integrated mixed-mode neural network architecture for megasynapse ANNs
Johannes Schemmel, F. Shurmann, Steffen Hohmann, Karlheinz Meier · 2003
This paper presents a new VLSI architecture for ANNs based on the combination of digital signalling and analog computing. It achieves a high level of parallelism as well as efficient area and power usage making very large networks possible. An implementation is presented combining 33k synapses and 256 neurons on 9 mm/sup 2/ of silicon area.