Implementing fair queueing in ATM switches. I. A practical methodology for the analysis of delay bounds
Fabio M. Chiussi, Andrea Francini · 2002
The minimization of the implementation cost of cell schedulers which aim at approximating the generalized processor sharing (GPS) policy is a key practical issue in next-generation ATM switches. The total complexity of a GPS-related scheduler is a combination of the complexity of its system-potential function and the complexity involved in sorting the timestamps in order to select which cell should be transmitted. Several scheduling disciplines using a system-potential function of O(1) complexity have previously been introduced; still, the task of sorting the timestamps makes the cost of implementing a GPS-related scheduler quite significant. Thus, in practice, approximations are often introduced in the scheduler to reduce implementation complexity, typically at the cost of some degradation in the delay properties of the scheduler. In order to optimize the design so that such degradations are minimized, a tool is necessary, in the form of a general methodology to promptly and accurately analyze the delay properties. To truly aid in the design of the scheduler, such methodology should be simple to use in all practical situations. We present a methodology that fulfills this need. In the case of leaky-bucket constrained sources, we explicitly derive a general result for the delay bounds; our methodology, however, is applicable to other source models.